Conventional analog-to-digital (A/D) converters of the sigma delta type use oversampling of an analog input signal in order to process the signal using low resolution components and digital filtering to obtain a digital representation of the analog input signal. Such A/D converters can be efficiently implemented in VLSI technologies because most of the circuit components are digital, and low-precision analog components are sufficient even for high accuracy conversions.
A general block diagram of a typical sigma-delta A/D converter is shown in FIG. 1. It consists of an analog front end 10, which is also called a sigma delta modulator, and a digital low pass filter 20. The analog input signal of bandwidth fc is sampled at a very high sampling rate, Fs, by the modulator 10. The ratio of Fs/(2fc) is called the over sampling ratio F. The output of the modulator 10 is typically a serial digital signal containing the digital representation of the analog signal along with quantization noise. The output of the modulator 10 is filtered by the digital low pass filter 20 to remove most of the quantization noise from the digital signal for frequencies higher than fc. Finally, the filtered digital signal can be sampled at the 2fc rate to represent the analog signal of bandwidth fc in the digital domain. The digital low pass filter 20 and output sampling are referred to as a "decimator" in the drawing.
As shown in FIG. 1, the sigma-delta modulator 10 generally consists of a sampling circuit a differencing circuit 12, an integrator 13 or analog filter, an A/D converter 14 of "L" bit resolution, and a feedback D/A converter 15 also of "L" bit resolution. The number L is typically one for a first-order sigma-delta modulator, which reduces the internal A/D converter to a simple comparator circuit 14' and the D/A converter to a pair of switches 15' connected to reference voltages +Vr and -Vr, as shown in FIG. 2.
The basic function of the sigma-delta modulator (analog front end) is to sample the analog input signal at a much higher rate than (typically 64 to 256 times) the analog input signal frequency and to produce a serial stream of output digital bits and words. The average value of the serial digital output is equal to the analog input signal due to the feedback circuit. Moreover, the integrator 13 or analog filter in the feedback loop shapes the quantization noise of the internal A/D converter. Thus, the spectrum of the serial digital output contains the analog input signal and the shaped quantization noise.
The shape of the quantization noise is such that a very small energy of the noise is in the baseband or signal bandwidth, and most of the energy of the noise is in the higher frequency region which is to be removed by the digital filter 20 of the decimator. Referring to FIG. 3, the quantized output of a first-order (one integrator in the feedback loop) sigma-delta modulator is shown for a sinusoidal analog input. The output is predominantly high when the input signal is close to its peak and mostly low for signal valleys. The output appears to be a 50% duty cycle signal for the input signal close to zero.
In FIG. 4, the spectrum density of the output of the sigma-delta modulator is illustrated labelled as "before dec. (decimator) filter". The noise is shaped as a linear function of frequency due to there being one integrator in the modulator loop. A decimating low pass filter can remove the high frequency components of the noise, resulting in the final output spectrum labelled as "after dec. filter".
The basic function of the digital filter of the decimator is to remove the quantization noise from the output of the modulator 10. The output signal bandwidth is much smaller than the modulator sampling rate, so the output can be computed at a much slower rate (2fc) without loss of any information. Thus, the filter is called a low pass decimation filter as the sampling rate is down sampled from Fs to 2fc. The filtering is achieved using several stages. One type of filter is called a COMB filter, as illustrated in FIG. 5, which consists of an (N+1) cascade of integrators coupled, via a resampler at a sampling rate of Fs/F, to a (N+1) cascade of differentiators in order to implement the following filter transfer function: EQU H(Z)={1/F.times.(1-Z.sup.-F)/(1-Z.sup.-1)}.sup.N+1
The integrators operate at a high sampling rate Fs, whereas the differentiators operate at a much reduced rate of Fs/F, which is equal to 2fc. The cutoff frequency of the filter is kept at fc.
The accuracy of the analog to digital conversion is dependent on the oversampling ratio and topology of the modulator. The accuracy is calculated by computing the ratio of the signal to noise in the baseband fc of the filtered signal. A detailed analysis of such calculation is described in the paper "A Use of Double Integration in Sigma Delta Modulation", by James Candy, Bell Laboratories, in IEEE Trans. on Communications, Vol. COM-33, No. 3, March 1985. As an example, the signal spectrum of the first order system illustrated in FIG. 4 has the noise energy linearly increasing with frequency. Thus, if the bandwidth is reduced by oversampling, more than a linear proportion of the noise will be excluded. For example, a gain in signal-to-noise ratio of (9L-5.2) db, where L is the number of octaves of oversampling (oversampling ratio F=2.sup.L), is discussed in "Circuit and Technology Considerations for MOS Delta-Sigma A/D Converters", by Max Hauser and Robert Brodersen, University of California at Berkeley, in IEEE Publication CH2255-8/86, pp. 1310-1315, 1986. If the oversampling ratio is 64, or 6 octaves, then the signal-to-noise ratio will be 49 db or 8 bits. If the oversampling ratio is increased to 256, or 8 octaves, the signal-to-noise ratio is increased to 67 db or 11 bits of resolution. Thus, the accuracy is higher for higher values of the oversampling ratio as the noise is lowered in the baseband.
Another factor in the accuracy of the modulator is the shape of the noise. The first-order system has a linear shape for the noise spectrum due to the use of the one integrator in the modulator loop. Higher-order systems may have a plurality of integrators which gives the noise a more complex spectrum shape. For example, a second-order sigma-delta A/D converter is shown in FIG. 6 using two integrators 33A and 33B coupled to a comparator 34, a latch (FF) 35, and the digital low pass filter 20. The latch (FF) 35 is switched between reference voltages and acts as a one-bit DAC for feeding back the loop signal to the summing nodes A, B. The circuit operates at a clock corresponding to the sampling rate fs for optimum performance. The serial data from the modulator are provided at frequency fs to the filter. Thus, if the signal bandwidth is fc, the maximum oversampling ratio is F =fs/2fc.
The resulting spectrum of the output of the second-order system is shown in FIG. 7A having a square law characteristic. The second integrator further decreases the noise energy in the baseband compared to a first-order system, as shown in FIG. 7B. Thus, the improvement in signal-to-noise ratio, which is 9 db or 1.5 bits of resolution for each doubling of the oversampling ratio for the first-order system, is now 15 db or 2.5 bits for each doubling of the oversampling ratio for the second-order system. Similarly, the improvement in signal-to noise ratio for a third order system is 21 db/octave or 3.5 bits/octave. Generalizing this relationship, the improvement in signal-to-noise ratio for a N order system is (6N+3) db/octave or (0.5+N) bits/octave. A further discussion of oversampling as a technique for high resolution A/D conversion is given in "A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters", by Kirk Chao, et al., IEEE Trans. on Circuits and Systems, Vol. 37, No. 3, March 1990.
Another approach to obtaining higher-order noise-shaping is to cascade several first-order modulators. The first modulator converts the analog input signal, and the subsequent modulators convert the quantization noise generated by the previous modulator. The quantization errors of all but the last modulator are digitally cancelled, yielding a noise shaping function of order equal to the number of first-order modulators. Advantages of the cascaded sigma-delta approach include guaranteed stability to any order, limited signal swing at the output of the integrator, and pipelining of the integrators. The main disadvantage of the cascaded technique is that the S/N ratio is more sensitive to analog component accuracy. A further discussion of cascaded sigma-delta modulators is provided in "A High-Resolution CMOS Sigma-Delta A/D Converter", by Mike Rebeschini, et al., IEEE Publication CH2692-2/89, pp. 246-249, 1989.
One implementation of the higher-order modulator employs switched-capacitor couplings between integrators. An example of a second-order switched-capacitor sigma-delta modulator is shown in FIG. 8A having two integrator stages 40, A/D comparator 44, and switched-capacitor couplings. The comparator is switched with a clock at the sampling rate fs. The output spectrum and noise shape are similar to those shown in FIGS. 7A and 7B. A further discussion of switched-capacitor sigma-delta systems is provided in "Delta-Sigma A/Ds with Reduced Sensitivity to Op Amp Noise and Gain", by Paul Hurst, et al., lEEE publication CH2692-2/89, pp. 254-257, 1989.
Thus, the prior art has taken the approach of using higher-order modulators and higher sampling frequencies to obtain higher accuracy converters for processing wide bandwidth signals. However, only first-order systems are unconditionally stable. Second and multi-order systems have stability problems for some input conditions. The higher sampling systems use high oversampling ratios to obtain high precision converters for low bandwidth signals or dc levels. However, the sampling rate of the modulator is limited by the characteristics of the analog circuit components. Cascaded systems are commonly used, but have the problem that the S/N ratio is sensitive to analog component accuracy. Thus, new circuit techniques are needed to improve the effective sampling rate, speed, and accuracy of sigma-delta converters for better analog-to-digital performance, especially for high frequency applications and very high precision, low frequency applications.